View CY7C09099V-7AI_4298495.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

cy7c09079v/89v/99v cy7c09179v/89v/99v 3.3v 32k/64k/128k x 8/9 synchronous dual-port static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-06043 rev. *e revised december 14, 2010 features true dual-ported memory cells which enable simultaneous access of the same memory location 6 flow-through and pipelined devices 32k x 8/9 organizations (cy7c09079v/179v) 64k x 8/9 organizations (cy7c09089v/189v) 128k x 8/9 organizations (cy7c09099v/199v) 3 modes flow-through pipelined burst pipelined output mode on both ports enables fast 100 mhz operation 0.35-micron cmos for optimum speed and power high speed clock to data access 6.5[1]/7.5[1]/9/12 ns (max.) 3.3v low operating power active= 115 ma (typical) standby= 10 ? a (typical) fully synchronous interface for easier operation burst counters increment addresses internally shorten cycle times minimize bus noise supported in flow-through and pipelined modes dual chip enables for easy depth expansion automatic power down commercial and industrial temperature ranges available in 100-pin tqfp pb-free packages available notes 1. see page 6 for load conditions. 2. i/o 0 ?i/o 7 for x8 devices, i/o 0 ?i/o 8 for x9 devices. 3. a 0 ?a 14 for 32k, a 0 ?a 15 for 64k, and a 0 ?a 16 for 128k devices. logic block diagram r/w l ce 0l ce 1l oe l ft /pipe l i/o 0l ?i/o 7/8l control a 0 ?a 14/15/16l clk l ads l cnten l cntrst l r/w r 1 0 0/1 ce 0r ce 1r oe r 1 0/1 0 ft /pipe r i/o 0r ?i/o 7/8r i/o control a 0 ?a 14/15/16r clk r ads r cnten r cntrst r 1 0 0/1 1 0/1 0 i/o counter/ address register decode true dual-ported ram array counter/ address register decode 8/9 8/9 [2] [2] [3] [3] 15/16/17 15/16/17 cy7c09079v/89v/99v cy7c09179v/89v/99v [+] feedback
cy7c09079v/89v/99v cy7c09179v/89v/99v document #: 38-06043 rev. *e page 2 of 20 functional description the cy7c09079v/89v/99v a nd cy7c09179v/89v/99v are high speed synchronous cmos 32k, 64k, and 128k x 8/9 dual-port static rams. two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory. [4] registers on control, address, and data lines enable minimal setup and hold times. in pipelined output mode, data is registered for dec reased cycle time. clock to data valid t cd2 = 6.5 ns [1] (pipelined). flow-through mode can also be used to bypass the pipelined out put register to eliminate access latency. in flow-through mode, data is available t cd1 = 18 ns after the address is clocked into the device. pipelined output or flow-through mode is selected via the ft /pipe pin. each port contains a burst count er on the input address register. the internal write pulse width is independent of the low-to-high transition of the clock signal. the internal write pulse is self-timed to enable th e shortest possible cycle times. a high on ce 0 or low on ce 1 for one clock cycle powers down the internal circuitry to reduce the static power consumption. the use of multiple chip enables enables easier banking of multiple chips for depth expansion configurations. in the pipelined mode, one cycle is required with ce 0 low and ce 1 high to reactivate the outputs. counter enable inputs are provided to stall the operation of the address input and use the internal address generated by the internal counter for fast interleaved memory applications. a port?s burst counter is loaded with the port?s address strobe (ads ). when the port?s count enable (cnten ) is asserted, the address counter increments on each low-to-high transition of that port?s clock signal. this reads/writes one word from/into each successive address location until cnten is deasserted. the counter can address the entire memory array and loops back to the start. counter reset (cntrst ) is used to reset the burst counter. all parts are available in 100-pin thin quad plastic flatpack (tqfp) packages. pin configurations figure 1. 100-pin tqfp (top vi ew) - cy7c09099v (128k x 8), cy7c09089v (64k x 8),cy7c09079v (32k x 8) notes 4. when writing simultaneously to the same location, the final value cannot be guaranteed. 5. this pin is nc for cy7c09079v. 6. this pin is nc for cy7c09079v and cy7c09089v. 7. for cy7c09079v and cy7c09089v, pin #23 connected to v cc is pin compatible with an idt 5v x8 pipelined device; connecting pin #23 and #53 to gnd is pin compatible with an idt 5v x16 flow-through device. 1 3 2 92 91 90 84 85 87 86 88 89 83 82 81 76 78 77 79 80 93 94 95 96 97 98 99 100 59 60 61 67 66 64 65 63 62 68 69 70 75 73 74 72 71 nc nc a7r a8r a9r a10r a15r a12r a14r gnd nc nc ce 0r a13r a11r nc nc ce1r cntrst r r/wr oe r ft /piper gnd nc a16r 58 57 56 55 54 53 52 51 nc nc a7l a8l a9l a10l a15l a12l a14l vcc nc nc ce 0l a13l a11l nc nc ce1l cntrst l r/w l oe l ft /pipel nc nc a16l 17 16 15 9 10 12 11 13 14 8 7 6 4 5 18 19 20 21 22 23 24 25 nc nc a6l a5l a4l a3l clkl a1l cntenl gnd adsr a0r a1r a0l a2l clkr cntenr a2r a3r a4r a5r a6r nc nc adsl 34 35 36 42 41 39 40 38 37 43 44 45 50 48 49 47 46 nc nc nc i/o7r i/o6r i/o5r i/01r i/o3r i/o2r gnd vcc gnd i/o2l vcc i/o4r i/o0l i/o1l i/o3l i/o4l i/o5l i/o6l i/o7l nc gnd i/o0r 33 32 31 30 29 28 27 26 [5] [5] [6] [6] [7] [7] [+] feedback
cy7c09079v/89v/99v cy7c09179v/89v/99v document #: 38-06043 rev. *e page 3 of 20 pin configurations (continued figure 2. 100-pin tqfp (top view0 - cy7c09199v ( 128k x 9), cy7c09189v (64k x 9),cy7c09179v (32k x 9) 1 3 2 92 91 90 84 85 87 86 88 89 83 82 81 76 78 77 79 80 93 94 95 96 97 98 99 100 59 60 61 67 66 64 65 63 62 68 69 70 75 73 74 72 71 nc nc a7r a8r a9r a10r a15r a12r a14r gnd nc nc ce 0r a13r a11r nc nc ce1r cntrst r r/wr oe r ft /piper gnd nc a16r 58 57 56 55 54 53 52 51 nc nc a7l a8l a9l a10l a15l a12l a14l vcc nc nc ce 0l a13l a11l nc nc ce1l cntrst l r/w l oe l ft /pipel nc nc a16l 17 16 15 9 10 12 11 13 14 8 7 6 4 5 18 19 20 21 22 23 24 25 nc nc a6l a5l a4l a3l clkl a1l cntenl gnd gnd cntenr a0r a0l a2l adsr clkr a1r a2r a3r a4r a5r a6r nc adsl 34 35 36 42 41 39 40 38 37 43 44 45 50 48 49 47 46 nc nc i/o8r i/o7r i/o6r i/o5r i/01r i/o3r i/o2r gnd vcc gnd i/o2l vcc i/o4r i/o0l i/o1l i/o3l i/o4l i/o5l i/o6l i/o7l i/o8l gnd i/o0r 33 32 31 30 29 28 27 26 [8] [8] [9] [9] [+] feedback
cy7c09079v/89v/99v cy7c09179v/89v/99v document #: 38-06043 rev. *e page 4 of 20 notes 8. this pin is nc for cy7c09179v. 9. this pin is nc for cy7c09179v and cy7c09189v selection guide description cy7c09079v/89v/99v cy7c09179v/89v/99v-6 [1] cy7c09079v/89v/99v cy7c09179v/89v/99v-7 [1] cy7c09079v/89v/99v cy7c09179v/89v/99v -9 cy7c09079v/89v/99v cy7c09179v/89v/99v -12 f max2 (mhz) (pipelined) 100 83 67 50 max. access time (ns) (clock to data, pipelined) 6.5 7.5 9 12 typical operating current i cc (ma) 175 155 135 115 typical standby current for i sb1 (ma) (both ports ttl level) 25 25 20 20 typical standby current for i sb3 ( ? a) (both ports cmos level) 10 ? a 10 ? a10 ? a 10 ? a pin definitions left port right port description a 0l ?a 16l a 0r ?a 16r address inputs (a 0 ?a 14 for 32k; a 0 ?a 15 for 64k; and a 0 ?a 16 for 128k devices). ads l ads r address strobe input. used as an address qual ifier. this signal should be asserted low to access the part using an externally supplied address. asserting this signal low also loads the burst counter with the addr ess present on the address pins. ce 0l ,ce 1l ce 0r ,ce 1r chip enable input. to select either the left or right port, both ce 0 and ce 1 must be asserted to their active states (ce 0 ? v il and ce 1 ?? v ih ). clk l clk r clock signal. this input can be free running or strobed. maximum cl ock input rate is f max . cnten l cnten r counter enable input. asserting this signal lo w increments the burst address counter of its respective port on each rising edge of clk. cnten is disabled if ads or cntrst are asserted low. cntrst l cntrst r counter reset input. asserting this signal low resets the burst address counter of its respective port to zero. cntrst is not disabled by asserting ads or cnten . i/o 0l ?i/o 8l i/o 0r ?i/o 8r data bus input/output (i/o 0 ?i/o 7 for x8 devices; i/o 0 ?i/o 8 for x9 devices). oe l oe r output enable input. this signal must be asse rted low to enable the i/o data pins during read operations. r/w l r/w r read/write enable input. this si gnal is asserted low to write to the dual port memory array. for read operations, assert this pin high. ft /pipe l ft /pipe r flow-through/pipelined select input. for flow-t hrough mode operation, assert this pin low. for pipelined mode operation, assert this pin high. gnd ground input. nc no connect. v cc power input. [+] feedback
cy7c09079v/89v/99v cy7c09179v/89v/99v document #: 38-06043 rev. *e page 5 of 20 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. [10] storage temperature ................................. ?65 ? c to +150 ? c ambient temperature wit h power applied.. ?55 ? c to +125 ? c supply voltage to ground potentia l................?0.5v to +4.6v dc voltage applied to outputs in high z state ....... .................... ?0.5v to v cc +0.5v dc input voltage ..................................... ?0.5v to v cc +0.5v output current into outputs (low)............................. 20 ma static discharge voltage....... ........... ............ .............. >2001v latch-up current ..................................................... >200 ma operating range range ambient temperature v cc commercial 0 ? c to +70 ? c 3.3v ? 300 mv industrial [11] ?40 ? c to +85 ? c 3.3v ? 300 mv notes 10. the voltage on any input or i/o pin cannot exceed the power pin during power-up. 11. industrial parts are available in cy7c09099v and cy7c09199v only. 12. ce l and ce r are internal signals. to select either the left or right port, both ce 0 and ce 1 must be asserted to their active states (ce 0 ? v il and ce 1 ?? v ih ). electrical characteristics over the operating range parameter description cy7c09079v/89v/99v cy7c09179v/89v/99v unit -6 [1] -7 [1] -9 -12 min typ max min typ max min typ max min typ max v oh output high voltage (v cc = min. i oh = ?4.0 ma) 2.4 2.4 2.4 2.4 v v ol output low voltage (v cc = min. i oh = +4.0 ma) 0.4 0.4 0.4 0.4 v v ih input high voltage 2.0 2.0 2.0 2.0 v v il input low voltage 0.8 0.8 0.8 0.8 v i oz output leakage current ?10 10 ?10 10 ?10 10 ?10 10 ? a i cc operating current (v cc = max. i out = 0 ma) outputs disabled commercial. 175 320 155 275 135 225 115 205 ma industrial [11] 275 390 185 295 ma i sb1 standby current (both ports ttl level) [12] ce l & ce r ? v ih , f = f max commercial. 25 95 25 85 20 65 20 50 ma industrial [11] 85 120 35 75 ma i sb2 standby current (one port ttl level) [12] ce l | ce r ? v ih , f = f max commercial. 115 175 105 165 95 150 85 140 ma industrial [11] 165 210 105 160 ma i sb3 standby current (both ports cmos level) [12] ce l & ce r ? v cc ? 0.2v, f = 0 commercial. 10 250 10 250 10 250 10 250 ? a industrial [11] 10 250 10 250 ? a i sb4 standby current (one port cmos level) [12] ce l | ce r ? v ih , f = f max commercial 105 135 95 125 85 115 75 100 ma industrial [11] 125 170 95 125 ma capacitance parameter description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 3.3v 10 pf c out output capacitance 10 pf [+] feedback
cy7c09079v/89v/99v cy7c09179v/89v/99v document #: 38-06043 rev. *e page 6 of 20 figure 4. ac test loads (applicable to -6 and -7 only) [13] figure 5. load derating curve figure 3. ac test loads (a) normal load (load 1) r1 = 590 ? 3.3v output r2 = 435 ? c= 30 pf v th =1.4v output c= 30 pf (b) thvenin equivalent (load 1) (c) three-state delay (load 2) r1 = 590 ? r2 = 435 ? 3.3v output c= 5pf r th = 250 ? (used for t cklz , t olz , & t ohz including scope and jig) v th =1.4v output c (a) load 1 (-6 and -7 only) r = 50 ? z 0 = 50 ? 3.0v gnd 90% 90% 10% 3ns 3 ns 10% all input pulses ? ? 0.00 0.1 0 0.20 0.30 0.40 0.50 0.60 1 0 1 5 20 25 30 35 capacitance (pf) ?? (ns) for all -7 access times note 13. test conditions: c = 10 pf. [+] feedback
cy7c09079v/89v/99v cy7c09179v/89v/99v document #: 38-06043 rev. *e page 7 of 20 notes 14. test conditions used are load 2. 15. this parameter is guaranteed by design, but it is not production tested. switching characteristics over the operating range parameter description cy7c09079v/89v/99v cy7c09179v/89v/99v unit -6 [1] -7 [1] -9 -12 min max min max min max min max f max1 f max flow-through 53 45 40 33 mhz f max2 f max pipelined 100 83 67 50 mhz t cyc1 clock cycle time - flow-through 19 22 25 30 ns t cyc2 clock cycle time - pipelined 10 12 15 20 ns t ch1 clock high time - flow-through 6.5 7.5 12 12 ns t cl1 clock low time - flow-through 6.5 7.5 12 12 ns t ch2 clock high time - pipelined 4 5 6 8 ns t cl2 clock low time - pipelined 4 5 6 8 ns t r clock rise time 3 3 3 3 ns t f clock fall time 3 3 3 3 ns t sa address set-up time 3.5 4 4 4 ns t ha address hold time 0 0 1 1 ns t sc chip enable set-up time 3.5 4 4 4 ns t hc chip enable hold time 0 0 1 1 ns t sw r/w set-up time 3.5 4 4 4 ns t hw r/w hold time 0 0 1 1 ns t sd input data set-up time 3.5 4 4 4 ns t hd input data hold time 0 0 1 1 ns t sad ads set-up time 3.5 4 4 4 ns t had ads hold time 0 0 1 1 ns t scn cnten set-up time 3.5 4.5 5 5 ns t hcn cnten hold time 0 0 1 1 ns t srst cntrst set-up time 3.5 4 4 4 ns t hrst cntrst hold time 0 0 1 1 ns t oe output enable to data valid 8 9 10 12 ns t olz [14, 15] oe to low z 2 2 2 2 ns t ohz [14, 15] oe to high z 1 7 1 7 1 7 1 7 ns t cd1 clock to data valid - flow-through 15 18 20 25 ns t cd2 clock to data valid - pipelined 6.5 7.5 9 12 ns t dc data output hold after clock high 2 2 2 2 ns t ckhz [14, 15] clock high to output high z 2 9 2 9 2 9 2 9 ns t cklz [14, 15] clock high to output low z 2 2 2 2 ns port to port delays t cwdd write port clock high to read data delay 30 35 40 40 ns t ccs clock to clock set-up time 9 10 15 15 ns [+] feedback
cy7c09079v/89v/99v cy7c09179v/89v/99v document #: 38-06043 rev. *e page 8 of 20 switching waveforms (continued) figure 6. read cycle for flow-through output (ft /pipe = v il ) [16, 17, 18, 19] notes 16. oe is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 17. ads = v il , cnten and cntrst = v ih . 18. the output is disabled (high-impedance state) by ce 0 =v ih or ce 1 = v il following the next rising edge of the clock. 19. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk. numbers are for reference only. t ch1 t cl1 t cyc1 t sc t hc t dc t ohz t oe t sc t hc t sw t hw t sa t ha t cd1 t ckhz t dc t olz t cklz a n a n+1 a n+2 a n+3 q n q n+1 q n+2 clk ce 0 ce 1 r/w address data out oe [+] feedback
cy7c09079v/89v/99v cy7c09179v/89v/99v document #: 38-06043 rev. *e page 9 of 20 figure 7. read cycle for pipelined operation (ft /pipe = v ih ) [16, 17, 18, 19] figure 8. bank select pipelined read [20, 21] - switching waveforms (continued) t ch2 t cl2 t cyc2 t sc t hc t sw t hw t sa t ha a n a n+1 clk ce 0 ce 1 r/w address data out oe a n+2 a n+3 t sc t hc t ohz t oe t olz t dc t cd2 t cklz q n q n+1 q n+2 1 latency d 3 d 1 d 0 d 2 a 0 a 1 a 2 a 3 a 4 a 5 d 4 a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha t sc t hc t sa t ha t sc t hc t sc t hc t sc t hc t ckhz t dc t dc t cd2 t cklz t cd2 t cd2 t ckhz t cklz t cd2 t ckhz t cklz t cd2 t ch2 t cl2 t cyc2 clk l address (b1) ce 0(b1) data out(b2) data out(b1) address (b2) ce 0(b2) [+] feedback
cy7c09079v/89v/99v cy7c09179v/89v/99v document #: 38-06043 rev. *e page 10 of 20 figure 9. left port write to flow-through right port read [22, 23, 24, 25] notes 20. in this depth expansion example, b1 repr esents bank #1 and b2 is bank #2; each ba nk consists of one cypress dual-port device from this datasheet. address (b1) = address (b2) . 21. oe and ads = v il ; ce 1(b1) , ce 1(b2) , r/w , cnten , and cntrst = v ih . 22. the same waveforms apply for a right port write to flow-through left port read. 23. ce 0 and ads = v il ; ce 1 , cnten , and cntrst = v ih . 24. oe = v il for the right port, which is being read from. oe = v ih for the left port, which is being written to. 25. it t ccs ? maximum specified, then data from right port read is not valid until the maximum specified for t cwdd . if t ccs >maximum specified, then data is not valid until t ccs + t cd1 . t cwdd does not apply in this case. switching waveforms (continued) t sa t ha t sw t hw t sd t hd match valid t ccs t sw t hw t dc t cwdd t cd1 match t sa t ha match no match no valid valid t dc t cd1 clk l r/w l address l data inl address r data outr clk r r/w r [+] feedback
cy7c09079v/89v/99v cy7c09179v/89v/99v document #: 38-06043 rev. *e page 11 of 20 figure 10. pipelined read-to-write-to-read (oe = v il ) [19, 26, 27, 28] switching waveforms (continued) t cyc2 t cl2 t ch2 t hc t sc t hw t sw t ha t sa t hw t sw t cd2 t ckhz t sd t hd t cklz t cd2 no operation write read read clk ce 0 ce 1 r/w address data in data out a n a n+1 a n+2 a n+2 d n+2 a n+3 a n+4 q n q n+3 [+] feedback
cy7c09079v/89v/99v cy7c09179v/89v/99v document #: 38-06043 rev. *e page 12 of 20 figure 11. pipelined r ead-to-write-to-read (oe controlled) [19, 26, 27, 28] notes 26. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 27. ce 0 and ads = v il ; ce 1 , cnten , and cntrst = v ih . 28. during ?no operation?, data in memory at the selected address may be corrupted and should be re-written to ensure data integ rity. switching waveforms (continued) t cyc2 t cl2 t ch2 t hc t sc t hw t sw t ha t sa a n a n+1 a n+2 a n+3 a n+4 a n+5 t hw t sw t sd t hd d n+2 t cd2 t ohz read read write d n+3 t cklz t cd2 q n q n+4 clk ce 0 ce 1 r/w address data in data out oe [+] feedback
cy7c09079v/89v/99v cy7c09179v/89v/99v document #: 38-06043 rev. *e page 13 of 20 figure 12. flow-through read-to-write-to-read (oe = v il ) [17, 19, 26, 27, 28] figure 13. flow-through read-to-write-to-read (oe controlled) [17, 20, 26, 27, 28] switching waveforms (continued) t ch1 t cl1 t cyc1 t sc t hc t sw t hw t sa t ha t sw t hw t sd t hd a n a n+1 a n+2 a n+2 a n+3 a n+4 d n+2 q n q n+1 q n+3 t cd1 t cd1 t dc t ckhz t cd1 t cd1 t cklz t dc read no operation write read clk ce 0 ce 1 address r/w data in data out q n t ch1 t cl1 t cyc1 t sc t hc t sw t hw t sa t ha t cd1 t dc t ohz read a n a n+1 a n+2 a n+3 a n+4 a n+5 d n+2 d n+3 t sw t hw t sd t hd t cd1 t cd1 t cklz t dc q n+4 t oe write read clk ce 0 ce 1 address r/w data in data out oe [+] feedback
cy7c09079v/89v/99v cy7c09179v/89v/99v document #: 38-06043 rev. *e page 14 of 20 figure 14. pipelined read with address counter advance [29] figure 15. flow-through read with address counter advance [29] note 29. ce 0 and oe = v il ; ce 1 , r/w and cntrst = v ih . switching waveforms (continued) counter hold read with counter t sa t ha t sad t had t scn t hcn t ch2 t cl2 t cyc2 t sad t had t scn t hcn q x-1 q x q n q n+1 q n+2 q n+3 t dc t cd2 read with counter read external address clk address ads data out cnten a n t ch1 t cl1 t cyc1 t sa t ha t sad t had t scn t hcn a n t sad t had t scn t hcn clk address ads cnten q x q n q n+1 t dc counter hold read with counter read external address read with counter q n+3 q n+2 data out t cd1 [+] feedback
cy7c09079v/89v/99v cy7c09179v/89v/99v document #: 38-06043 rev. *e page 15 of 20 figure 16. write with address counter advance (flow-through or pipelined outputs) [30, 31] notes 30. ce 0 and r/w = v il ; ce 1 and cntrst = v ih . 31. the ?internal address? is equal to the ?external address? when ads = v il and equals the counter output when ads = v ih . switching waveforms (continued) t ch2 t cl2 t cyc2 a n a n+1 a n+2 a n+3 a n+4 d n+1 d n+1 d n+2 d n+3 d n+4 a n d n t sad t had t scn t hcn t sd t hd write external write with counter address write with counter write counter hold clk address internal cnten ads data in address t sa t ha [+] feedback
cy7c09079v/89v/99v cy7c09179v/89v/99v document #: 38-06043 rev. *e page 16 of 20 figure 17. counter reset (pipelined outputs) [19, 26, 32, 33] notes 32. ce 0 = v il ; ce 1 = v ih . 33. no dead cycle exists durin g counter reset. a read or write cycle ma y be coincidental wit h the counter reset. switching waveforms (continued) t ch2 t cl2 t cyc2 clk address internal cnten ads data in address cntrst r/w data out q 0 q 1 q n d 0 a x 01a n a n+1 t sad t had t scn t hcn t srst t hrst t sd t hd t sw t hw a n a n+1 t sa t ha counter reset write address 0 read address 0 read address 1 read address n [+] feedback
cy7c09079v/89v/99v cy7c09179v/89v/99v document #: 38-06043 rev. *e page 17 of 20 table 1. read/write and enable operation [34, 35, 36] inputs outputs oe clk ce 0 ce 1 r/w i/o 0 ? i/o 9 operation x h x x high-z deselected [37] x x l x high-z deselected [37] x l h l d in write l l h h d out read [37] h x l h x high-z outputs disabled table 2. address counter control operation [34, 38, 39, 40] address previous address clk ads cnten cntrst i/o mode operation x x x x l d out(0) reset counter reset to address 0 a n x l x h d out(n) load address load into counter x a n h h h d out(n) hold external address blocked?counter disabled x a n h l h d out(n+1) increment counter enabled?internal address generation notes 34. ?x? = ?don?t care?, ?h? = v ih , ?l? = v il . 35. ads , cnten , cntrst = ?don?t care.? 36. oe is an asynchronous input signal. 37. when ce changes state in the pipelined mode, deselection and read happen in the following clock cycle. 38. ce 0 and oe = v il ; ce 1 and r/w = v ih . 39. data shown for flow-through mode; pipelined mode output will be delayed by one cycle. 40. counter operation is independent of ce 0 and ce 1 . [+] feedback
cy7c09079v/89v/99v cy7c09179v/89v/99v document #: 38-06043 rev. *e page 18 of 20 ordering information the following table contains only the parts that are currently av ailable. if you do not see what you are looking for, contact y our local sales representative. for more inform ation, visit the cypress website at www.cypress.com and refer to the product summary page at http://www.cypre ss.com/products cypress maintains a worldwide network of offices, solution cent ers, manufacturer?s representativ es and distributors. to find th e office closest to you, visit us at http://www.cypress.com /go/datasheet/offices. ordering code definitions 64k x8 3.3v synchronous dual-port sram speed (ns) ordering code package name package type operating range 12 cy7c09089v-12axi a100 100-pin pb-free thin quad flat pack industrial 128k x8 3.3v synchronous dual-port sram speed (ns) ordering code package name package type operating range 7.5 [1] cy7c09099v-7axi a100 100-pin pb-free thin quad flat pack industrial 12 cy7c09099v-12axc a100 100-pin pb-free thin quad flat pack commercial 32k x9 3.3v synchronous dual-port sram speed (ns) ordering code package name package type operating range 6.5 [1] cy7c09179v-6axc a100 100-pin pb-free thin quad flat pack commercial 12 cy7c09179v-12axc a100 100-pin pb-free thin quad flat pack commercial 128k x9 3.3v synchronous dual-port sram speed (ns) ordering code package name package type operating range 9 cy7c09199v-9axc a100 100-pin pb-free thin quad flat pack commercial temperature range: x = c or i c = commercial; i = industrial x = pb-free (rohs compliant) package type: a = 100-pin tqfp speed grade: 12 ns or 6.5 ns or 7.5 ns or 9 ns v = 3.3 v x9 = depth: x = 7 or 8 or 9 7 = 32k; 8 = 64k; 9 = 128k x = width: x = 0 or 1 0 = 8; 1 = 9 09 = sync 7c = dual port sram cy = cypress device 7c cy 09 v - xx x x x x x9 [+] feedback
cy7c09079v/89v/99v cy7c09179v/89v/99v document #: 38-06043 rev. *e page 19 of 20 package diagram figure 18. 100-pin thin plastic quad flat pack (tqfp) a100 (51-85048) 51-85048 *d [+] feedback
document #: 38-06043 rev. *e revised december 14, 2010 page 20 of 20 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c09079v/89v/99v cy7c09179v/89v/99v ? cypress semiconductor corporation, 2001-2010. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com psoc solutions general psoc.cypress.com/solutions low power/low voltage psoc.cypress.com/low-power precision analog psoc.cypress.com/precision-analog lcd drive psoc.cypress.com/lcd-drive can 2.0b psoc.cypress.com/can usb psoc.cypress.com/usb document title: cy7c09079v/89v/99v, cy7c09179v/89v/99v 3.3v 32k /64k/128k x 8/9synchronous dual port static ram document number: 38-06043 rev. ecn no. orig. of change orig. of change description of change ** 110191 szv 09/29/01 change from spec number: 38-00667 to 38-06043 *a 122293 rbi 12/27/02 power up requirements added to operating conditions information *b 365034 pcn see ecn added pb-free logo added pb-free part ordering information: cy7c09089v-6axc, cy7c09089v-12axc, cy7c09099v-6axc, CY7C09099V-7AI, cy7c09099v-7axi, cy7c09099v-12axc, cy7c09179v-6axc, cy7c09179v-12axc, cy7c09189v-6axc, cy7c09189v-12axc, cy7c09199v-6axc, cy7c09199v-7axc, cy7c09199v-9axc, cy7c09199v-9axi, cy7c09199v-12axc *c 2623658 vkn/pyrs 12/17/08 added cy7c09089v-12axi part in the ordering information table *d 2897159 rame 03/22/10 removed inactive parts fr om ordering information table. updated package diagram. added note in ordering information section. *e 3110406 admu 12/14/2010 updated ordering information . added ordering code definitions . [+] feedback

▲Up To Search▲

Price & Availability of CY7C09099V-7AI

	To Download CY7C09099V-7AI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .